VLSI Digital Design using VHDL and Hardware:Handson

A Complete RTL Package

Description 

Course Description:

This course is a thorough introduction to the VHDL language. VHDL (VHSIC Hardware Description Language) is a versatile and powerful hardware description language which is used for modeling electronic systems at different levels of design abstraction.  This provides a foundation in RTL and test bench coding styles needed by design and verification engineers who are new to VHDL. This Sessions addresses targeting Xilinx FPGA devices to make sure you understand the whole process from simulation to FPGA. There is a lecture section for each main topic.  Lectures contain numerous examples that show both syntax and coding style. This presents a basic foundation for the language. The Knowledge gained can be applied to any digital design by using a top-down or Bottom-up synthesis design approach. This course combines lectures with lab exercises to strengthen key concepts.

Objective:

The Main goal of this course is give you an overview of the VHDL language and its use in logic designing including VHDL syntax , build models using language constructs such as assignment, process statements, if statements, case statements and loops and coding styles . To make you familiar with developing a RTL VHDL model to understand the synthesizable subset of VHDL and writing a verification test cases and User constraints files for that model.

Who should take this course?
This course is designed for designers who are new to VHDL and who wish to become familiar with the language with a particular emphasis on writing RTL code for synthesis. And Engineers who want to use VHDL effectively for modeling, design, and synthesis of digital designs.  

At the end of the course, students will be able to:

After the course students with little or no VHDL knowledge will finish this course empowered with the ability to write efficient hardware designs and perform high-level HDL simulations. and

  • Gain a strong foundation in VHDL RTL and test bench coding techniques.
  • Write VHDL RTL hardware designs using good coding practices.
  • Learn the synthesizable subset of VHDL.
  • Use types, overloading, and conversion functions from standard VHDL packages (std_logic_1164).
  • Distinguish coding for synthesis versus coding for simulation.
  • Know about VHDL constructs used in simulation and synthesis environments.
  • Write VHDL Bench s for simulation.
  • Target and optimize Xilinx FPGAs by using VHDL.
  • Run a timing simulation by using Xilinx  ISim  libraries.
  • Create and manage designs within the Xilinx Design Suite.
  • Correctly model combinational and sequential hardware blocks.
  • Write User constraints files for any FPGA board.

What will students need to know or do before starting the course? :

  • Basic digital design knowledge

Software Tools

  • Download the Xilinx ISE Design suite 14.4 System Edition and Install In to your System.
  • Digilent NEXYS 2 Board   WITH Spartan 3E -500E or 1200 E .

Hardware

  • Digilent NEXYS 2 Board   WITH Spartan 3E -500E or 1200 E .
Who is the target audience?
  • This course is designed for designers who are new to VHDL and who wish to become familiar with the language with a particular emphasis on writing RTL code for synthesis. And Engineers who want to use VHDL effectively for modeling, design, and synthesis of digital designs.

Full Details : [ Take Course Now ]
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